DE 40 10 735 C 2 discloses a digital word-serial multiplying circuit. This serves for generating products of two bit-parallel binary signal values, which respectively contain bits of ascending order of significance, including a least significant bit and a most significant bit.
FIG. 1 shows an addition circuit for digital data with a saturation circuit. The addition circuit serves for the digital addition of two digital data values A, B. The data values A, B are in each case written to a clocked input register and have a predetermined data bit width n. The input registers A, B serve for the buffer storage of the input data A, B to be added and are respectively connected via n data lines to a data input of a digital adder ADD. The digital adder ADD is based on n full adders and has an n-bit-wide summation output to deliver the summation output data value formed by addition to a saturation circuit SAT. The saturation circuit SAT limits the present summation output data value within a data value range which is determined by an upper and a lower digital threshold value Smin, Smax. This achieves a clipping of the digital output signal. The summation output data value limited by the saturation circuit SAT is buffer-stored in a clocked output register and delivered for further data processing. The two input registers A, B and the output register are clocked by a clock signal CLK via a common clock line.
FIG. 2 shows timing diagrams of the signals within the conventional addition circuit, as it is represented in FIG. 1.
The conventional addition circuit receives the clock signal CLK with a predetermined clock period Tclk via a clock signal circuit. With the rising edge at the time t0, a data change takes place in the input data registers A, B, which are summed in the adder ADD. After a signal transit time, the summation output data value occurs at the output of the adder ADD as from the time t2. At the same time, a “glitching” takes place at the output of the adder ADD, i.e. the output data value fluctuates or changes until the final summation output data value has established itself. Glitches are disruptive pulses of short duration. The saturation circuit SAT receives the digital output signal, affected by disruptive pulses, from the adder ADD and delivers the unstable data to the output register between the times t3 and t5. The limited summation output data value fluctuates back and forth (“toggling”) during the time ΔT between the upper threshold value, the lower threshold value and the summation output value of the digital adder. Switching over between the upper threshold value and the minimum threshold value causes the data delivered by the saturation circuit SAT to have undergone a very high number of switching operations, resulting in a very high power loss in the saturation circuit SAT.